Z80230 데이터 시트보기 (PDF) - Zilog

부품명

상세내역

제조사

Z80230

Zilog SCC Serial Communication Controller

Zilog 

SCC™/ESCC™ User’s Manual

SCC/ESCC Ancillary Support Circuitry

3.2 BAUD RATE GENERATOR (Continued)

The time-constant can be changed at any time, but the

new value does not take effect until the next load of the

counter (i.e., after zero count is reached).

No attempt is made to synchronize the loading of a new

time-constant with the clock used to drive the generator.

When the time-constant is to be changed, the generator

should be stopped first by writing WR14 D0=0. After loading

the new time constant, the BRG can be started again. This

ensures the loading of a correct time constant, but loading

does not take place until zero count or a reset occurs.

If neither the transmit clock nor the receive clock are pro-

grammed to come from the /TRxC pin, the output of the

baud rate generator may be made available for external

use on the /TRxC pin.

Note: This feature is very useful for diagnostic purposes.

By programming the output of the baud rate generator as

output on the /TRxC pin, the BRG is source and time test-

ed, and the programmed time constant verified.

The clock source for the baud rate generator is selected by

bit D1 of WR14. When this bit is set to 0, the BRG uses the

signal on the /RTxC pin as its clock, independent of wheth-

er the /RTxC pin is a simple input or part of the crystal os-

cillator circuit. When this bit is set to 1, the BRG is clocked

by the PCLK. To avoid metastable problems in the

counter, this bit should be changed only while the baud

rate generator is disabled, since arbitrarily narrow pulses

can be generated at the output of the multiplexer when it

changes status.

The BRG is enabled while bit D0 of WR14 is set to 1. It is

disabled while WR14 D0=0 and after a hardware reset (but

not a software reset). To prevent metastable problems

when the baud rate generator is first enabled, the enable

bit is synchronized to the baud rate generator clock. This

introduces an additional delay when the baud rate

generator is first enabled (Figure 3-2). The baud rate

generator is disabled immediately when bit D0 of WR14 is

set to 0, because the delay is only necessary on start-up.

The baud rate generator is enabled and disabled on the fly,

but this delay on start-up must be taken into consideration.

Figure 3-2. Baud Rate Generator Start Up

3-2

UM010901-0601

Share Link: