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STM32F205RG 데이터 시트보기 (PDF) - STMicroelectronics

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STM32F205RG Datasheet PDF : 177 Pages
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STM32F20xxx
Application block diagrams
A.2 Application example with regulator OFF
Figure 84. Regulator OFF/internal reset ON
Power-down reset risen
after VCAP_1/VCAP_2 stabilization
Application reset signal
(optional)
Power-down reset risen
before VCAP_1/VCAP_2 stabilization
VCAP_1/2 monitoring
Application reset
Ext. reset controller active signal (optional)
when VCAP_1/2 < 1.08 V
VDD
(1.8 to 3.6 V)
PA0
VDD
NRST
VDD
(1.8 to 3.6 V)
PA0
VDD
NRST
1.2 V
REGOFF
VCAP_1
VCAP_2
1.2 V
REGOFF
VCAP_1 IRROFF
VCAP_2
ai18476
1. This mode is available only on UFBGA176 and WLCSP64+2 packages.
2. In regulator bypass mode, PA0 is used as power-on reset. The connection between PA0 and NRST can consequently
prevent debug connection. If the debug connection under reset or pre-reset is required, the user must manage the reset
and the power-on reset separately.
Figure 85. Regulator OFF/ internal reset OFF
VDD 1.2 V
1.2 V
VDD/VCAP_1/2 monitoring
Ext. reset controller active
when VDD < 1.65 V
and VCAP_1/2 < 1.08 V
NRST
REGOFF IRROFF
VDD
VCAP_1
VCAP_2
1. This mode is available only on WLCSP64+2 package.
VDD
(1.65 to 3.6 V)
VDD
ai18477
Doc ID 15818 Rev 9
157/177

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