STM32F407IGT7 데이터 시트보기 (PDF) - STMicroelectronics
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STM32F407IGT7 Datasheet PDF : 185 Pages
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Electrical characteristics
STM32F405xx, STM32F407xx
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 56 for the i2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Symbol
Table 56. I2S dynamic characteristics(1)
Parameter
Conditions
fMCK
I2S main clock output
-
fCK
I2S clock frequency
Master data: 32 bits
Slave data: 32 bits
DCK
I2S clock frequency duty cycle Slave receiver
tv(WS)
WS valid time
Master mode
th(WS)
WS hold time
Master mode
tsu(WS)
WS setup time
Slave mode
th(WS)
WS hold time
Slave mode
tsu(SD_MR) Data input setup time
tsu(SD_SR)
Master receiver
Slave receiver
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
Data input hold time
Data output valid time
Master receiver
Slave receiver
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
th(SD_MT) Data output hold time
Master transmitter (after enable edge)
1. Data based on characterization results, not tested in production.
2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency).
Min
256 x
8K
-
-
30
0
0
1
0
7.5
2
0
0
Max
256 x FS(2)
64 x FS
64 x FS
70
6
-
-
-
-
-
-
-
Unit
MHz
MHz
%
ns
-
27
-
20
2.5
-
Note:
Refer to the I2S section of RM0090 reference manual for more details on the sampling
frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The
value of these parameters might be slightly impacted by the source clock accuracy. DCK
depends mainly on the value of ODD bit. The digital contribution leads to a minimum value
of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV +
ODD). FS maximum value is supported for each mode/condition.
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