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STM32F407VEH6 데이터 시트보기 (PDF) - STMicroelectronics

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STM32F407VEH6 Datasheet PDF : 185 Pages
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STM32F405xx, STM32F407xx
Electrical characteristics
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
1.5
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
-
ns
tsu(Data_NE) Data to FSMC_NEx high setup time
THCLK+4
-
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
THCLK+4
-
ns
th(Data_NOE) Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
-
2
ns
tw(NADV)
FSMC_NADV low time
-
THCLK
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
FSMC_NEx
tw(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
FSMC_D[15:0]
FSMC_NADV(1)
tv(NWE_NE)
tw(NWE)
tv(A_NE)
tv(BL_NE)
tv(Data_NE)
t v(NADV_NE)
tw(NADV)
th(A_NWE)
Address
th(BL_NWE)
NBL
th(Data_NWE)
Data
t h(NE_NWE)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
3THCLK 3THCLK+ 4 ns
THCLK–0.5 THCLK+0.5 ns
THCLK–1
THCLK+2 ns
THCLK–1
-
ns
-
0
ns
DocID022152 Rev 4
139/185

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