Description
STM32F405xx, STM32F407xx
Figure 11. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
VDD
PDR = 1.7 V or 1.8 V (2)
V12
Min V12
VCAP_1/VCAP_2
NRST
PA0 asserted externally
time
2.2.17
2.2.18
1. This figure is valid both whatever the internal reset mode (onON or offOFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.
Regulator ON/OFF and internal reset ON/OFF availability
time ai18492d
Table 3. Regulator ON/OFF and internal reset ON/OFF availability
Regulator ON
Regulator OFF Internal reset ON
Internal reset
OFF
LQFP64
LQFP100
LQFP144
LQFP176
WLCSP90
UFBGA176
Yes
No
Yes
Yes
BYPASS_REG set BYPASS_REG set
to VSS
to VDD
Yes
Yes
PDR_ON set to
VDD
No
Yes
PDR_ON
connected to an
external power
supply supervisor
Real-time clock (RTC), backup SRAM and backup registers
The backup domain of the STM32F405xx and STM32F407xx includes:
• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
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DocID022152 Rev 4