PIC16F8X
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Clear f
[label] CLRF f
0 ≤ f ≤ 127
00h → (f)
1→Z
Z
00 0001 1fff ffff
The contents of register 'f' are cleared
and the Z bit is set.
1
1
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process Write
data register 'f'
Example
CLRF
FLAG_REG
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Z
=
0x5A
0x00
1
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Clear W
[ label ] CLRW
None
00h → (W)
1→Z
Z
00 0001 0xxx xxxx
W register is cleared. Zero bit (Z) is
set.
1
1
Q1
Q2
Q3
Q4
Decode No-Opera Process Write to
tion
data
W
Example
CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z=1
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
TO, PD
00 0000 0110 0100
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
1
1
Q1
Q2
Q3
Q4
Decode No-Opera Process
tion
data
Clear
WDT
Counter
Example
CLRWDT
Before Instruction
WDT counter =
After Instruction
WDT counter =
WDT prescaler=
TO
=
PD
=
?
0x00
0
1
1
DS30430C-page 58
© 1998 Microchip Technology Inc.