ADE3000SX 데이터 시트보기 (PDF) - STMicroelectronics

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ADE3000SX

LCD Display Engines with Integrated DVI, ADC and YUV Ports

STMicroelectronics 

ADE3XXX

Register Name

GLBL_CLK_SRC_SEL_2

GLBL_CLK_INV

GLBL_ANA_PWR

GLBL_XK_SRST

GLBL_I2C_CTRL

GLBL_XTAL_CTRL

Global Control Block

Table 4: Global Registers (Sheet 2 of 4)

Addr.

0x0002

Mode

R/W

R/W

0x0003

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x0005

R/W

R/W

R/W

R/W

R/W

0x0006

R/W

R/W

R/W

0x0007

R/W

R/W

R/W

0x0008

R/W

Bits

[7]

[6:4]

[3]

[2:0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7:5]

[4]

[3]

[2]

[1]

[0]

[7:3]

[2]

[1]

[0]

[7:3]

[2]

[1]

[0]

[7:1]

[0]

Default

Description

0x0 Reserved

0x4 LLK CTRL CLK source

0x0: YUVCLK pin

0x1: SCLK freq synth

0x2: LLKPLL control clock (normal)

0x3: CLKIN pin

0x4: crystal clock

0x5: 0

0x6 - 0x7: Reserved

Reserved

0x4 LLK ZERO CLK source

0x0: YUVCLK pin

0x1: SCLK freq synth

0x2: LLKPLL zero clock (normal)

0x3: CLKIN pin

0x4: crystal clock

0x5: 0

0x6 - 0x7: Reserved

0x0 Reserved

0x0 Invert YUV clock

0x0 Invert DVI detect clock

0x0 Invert ADC clock

0x0 Invert LLPLL zero clock

0x0 Invert LLPLL ctrl clock

0x0 Invert DOT clock

0x0 Invert input clock

0x0 Reserved

0x1 Blue ADC power down

0x1 Green ADC power down

0x1 Red ADC power down

0x1 DVI detect clock power down

0x1 DVI PLL power down

0x0 Reserved

0x0 SMEAS block reset, synchronous to XCLK

0x0 SRT block reset, synchronous to XCLK

0x0 Frame sync block reset, synchronous to

XCLK

0x0 Reserved

0x0 Disable I2C auto increment

0x0 SDA PMOS enable

0x0 Bypass I2C filter

0x0 Reserved

0x1 Crystal Oscillator Enable

15/88

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