ADP1043AACPZ-RL 데이터 시트보기 (PDF) - Analog Devices

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ADP1043AACPZ-RL

Digital Controller for Isolated Power Supply Applications

Analog Devices 

ADP1043A

THEORY OF OPERATION

CURRENT SENSE

The ADP1043A has two individual current sense inputs: CS1

and CS2±. These inputs sense, protect, and control the output

current and the share bus information. They can be calibrated

to remove any errors due to external components.

CS1 Operation (CS1)

CS1 is typically used for the monitoring and protection of the

primary side current. This is commonly known as the current

transformer (CT) method of current sensing. The input signal

at the CS1 pin is fed into an ADC for current monitoring. The

range of the ADC is 0 V to 1.38 V. The input signal is also fed

into a comparator for fast OCP protection. The typical config-

uration for the current sense is shown in Figure 10.

VIN

OUTA OUTC

OUTB OUTD

I = 10A

1V

CS1

1kΩ 10Ω I = 100mA

1:100

VREF

ADC 12 BITS

FAST

OCP

Figure 10. Current Sense 1 (CS1) Operation

The comparator effectively measures peak current, and the

ADC effectively measures the average current information.

This information is available through the I2C interface. Various

thresholds and limits can be set for CS1, such as OCP. These

thresholds and limits are described in the Current Sense and

Current Limit Registers section.

CS2 Operation (CS2+, CS2−)

CS2± is used for the monitoring and protection of the secondary

side current. The full-scale range of the CS2 ADC is 225 mV. The

nominal full load voltage drop can be configured for 37.5 mV,

75 mV, or 150 mV. The differential inputs are fed into an ADC

through a pair of external resistors. When using low-side current

sensing, a 10 kΩ resistor is required. When using high-side current

sensing, a 110 kΩ resistor is required (for a 12 V application).

Low-side current sensing is recommended because it provides

improved performance compared with high-side current sensing.

High-side current sensing is not supported for applications

where the output voltage is above 20 V common mode. (There

is not enough offset trim range above 20 V common mode.)

Typical configurations are shown in Figure 11 and Figure 12.

Various thresholds and limits can be set for CS2, such as OCP.

These thresholds and limits are described in the Current Sense

and Current Limit Registers section.

When not in use, both CS2 inputs should be connected through

10 kΩ resistors to PGND.

I

12V

110kΩ

CS2+

110kΩ

CS2–

1V

100µA

100µA

ADC 12 BITS

Figure 11. High-Side Resistive Current Sense

I

10kΩ

CS2–

10kΩ

CS2+

1V

100µA

100µA

ADC 12 BITS

Figure 12. Low-Side Resistive Current Sense (Recommended)

Rev. 0 | Page 12 of 72

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