C8051F045 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

12.1. Instruction Set

The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-

tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51

instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,

addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-

dard 8051.

12.1.1. Instruction and CPU Timing

In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with

machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based

solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.

Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock

cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock

cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 12.1 is the

CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock

cycles for each instruction.

12.1.2. MOVX Instruction and Program Memory

In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip

XRAM, and accessing on-chip program Flash memory. The Flash access feature provides a mechanism

for user software to update program code and use the program memory space for non-volatile data stor-

age (see Section “15. Flash Memory” on page 179). The External Memory Interface provides a fast

access to off-chip XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section

“16. External Data Memory Interface and On-Chip XRAM” on page 187 for details.

Mnemonic

ADD A, Rn

ADD A, direct

ADD A, @Ri

ADD A, #data

ADDC A, Rn

ADDC A, direct

ADDC A, @Ri

ADDC A, #data

SUBB A, Rn

SUBB A, direct

SUBB A, @Ri

SUBB A, #data

INC A

INC Rn

INC direct

INC @Ri

DEC A

Table 12.1. CIP-51 Instruction Set Summary

Description

Arithmetic Operations

Add register to A

Add direct byte to A

Add indirect RAM to A

Add immediate to A

Add register to A with carry

Add direct byte to A with carry

Add indirect RAM to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract indirect RAM from A with borrow

Subtract immediate from A with borrow

Increment A

Increment register

Increment direct byte

Increment indirect RAM

Decrement A

Bytes

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

1

Clock

Cycles

1

2

2

2

1

2

2

2

1

2

2

2

1

1

2

2

1

Rev. 1.5

129

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