C8051F045 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 12.13. EIE1: Extended Interrupt Enable 1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

CP2IE CP1IE CP0IE EPCA0 EWADC0 ESMB0 ESPI0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xE6

SFR Page: All Pages

Bit7:

Bit6:

Bit6:

Bit6:

Bit3:

Bit2:

Bit1:

Bit0:

Reserved. Read = 0b, Write = don’t care.

CP2IE: Enable Comparator (CP2) Interrupt.

This bit sets the masking of the CP2 interrupt.

0: Disable CP2 interrupts.

1: Enable interrupt requests generated by the CP2IF flag.

CP1IE: Enable Comparator (CP1) Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 interrupts.

1: Enable interrupt requests generated by the CP1IF flag.

CP0IE: Enable Comparator (CP0) Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 interrupts.

1: Enable interrupt requests generated by the CP0IF flag.

EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.

This bit sets the masking of the PCA0 interrupts.

0: Disable all PCA0 interrupts.

1: Enable interrupt requests generated by PCA0.

EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 Window Comparison interrupt.

0: Disable ADC0 Window Comparison Interrupt.

1: Enable Interrupt requests generated by ADC0 Window Comparisons.

ESMB0: Enable System Management Bus (SMBus0) Interrupt.

This bit sets the masking of the SMBus interrupt.

0: Disable all SMBus interrupts.

1: Enable interrupt requests generated by the SI flag.

ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.

This bit sets the masking of SPI0 interrupt.

0: Disable all SPI0 interrupts.

1: Enable Interrupt requests generated by the SPI0 flag.

Rev. 1.5

159

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