C8051F317 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F317

8/16 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F310/1/2/3/4/5/6/7

SCK*

MISO

T

MCKH

T

MCKL

T

MIS

T

MIH

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 16.8. SPI Master Timing (CKPHA = 0)

SCK*

MISO

T

MCKH

T

MCKL

T

MIS

T

MIH

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 16.9. SPI Master Timing (CKPHA = 1)

Rev. 1.6

179

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