C8051F38B-GMR 데이터 시트보기 (PDF) - Silicon Laboratories
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C8051F38B-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
26.4.2. 8-bit Timers with Auto-Reload
When T4SPLIT is 1 and T4CE = 0, Timer 4 operates as two 8-bit timers (TMR4H and TMR4L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 26.13. TMR4RLL holds the reload value for
TMR4L; TMR4RLH holds the reload value for TMR4H. The TR4 bit in TMR4CN handles the run control for
TMR4H. TMR4L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 4 Clock Select bits (T4MH and T4ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 4 External Clock Select bit (T4XCLK in TMR4CN), as follows:
T4MH
0
0
1
T4XCLK
0
1
X
TMR4H Clock Source
SYSCLK/12
External Clock/8
SYSCLK
T4ML
0
0
1
T4XCLK
0
1
X
TMR4L Clock Source
SYSCLK/12
External Clock/8
SYSCLK
The TF4H bit is set when TMR4H overflows from 0xFF to 0x00; the TF4L bit is set when TMR4L overflows
from 0xFF to 0x00. When Timer 4 interrupts are enabled, an interrupt is generated each time TMR4H over-
flows. If Timer 4 interrupts are enabled and TF4LEN (TMR4CN.5) is set, an interrupt is generated each
time either TMR4L or TMR4H overflows. When TF4LEN is enabled, software must check the TF4H and
TF4L flags to determine the source of the Timer 4 interrupt. The TF4H and TF4L interrupt flags are not
cleared by hardware and must be manually cleared by software.
T4XCLK
SYSCLK / 12
0
External Clock / 8
1
CKCON1
TTTT
5544
MMMM
HLHL
0
TR4
1
SYSCLK
TMR4RLH Reload
TCLK TMR4H
TMR4RLL Reload
To ADC
TF4H
TF4L
TF4LEN
T4CE
T4SPLIT
TR4
T4CSS
T4XCLK
1
TCLK TMR4L
0
Figure 26.13. Timer 4 8-Bit Mode Block Diagram
Interrupt
Rev. 1.4
289
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