CS4265-DNZ 데이터 시트보기 (PDF) - Cirrus Logic
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CS4265-DNZ Datasheet PDF : 56 Pages
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CS4265
6.4.3
6.4.4
6.4.5
ADC_DIF
0
1
Description
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Format
0
1
Mute ADC (Bit 2)
Table 9. ADC Digital Interface Formats
Figure
5
6
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 25.
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5 MCLK Frequency - Address 05h
7
Reserved
6
MCLK
Freq2
5
MCLK
Freq1
4
MCLK
Freq0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
6.5.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 10 for the appropriate settings.
MCLK Divider
÷1
÷ 1.5
MCLK Freq2
0
0
MCLK Freq1
0
0
MCLK Freq0
0
1
÷2
0
1
0
÷3
0
1
1
÷4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 10. MCLK Frequency
38
DS657F2
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