CS42324 데이터 시트보기 (PDF) - Cirrus Logic

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CS42324

10-In, 6-Out, 2 Vrms Audio CODEC

Cirrus Logic 

6.6.2

ADC Serial Port Source

This bit selects which serial port provides the sub clocks for the ADC.

ADC_SP

0

1

Serial Port 1 (SCLK1/LRCK1)

Serial Port 2 (SCLK2/LRCK2)

ADC sub clock source

CS42324

6.6.3

ADC Digital Interface Format (ADC_DIF)

These bits configure the serial audio interface format for transmitting digital audio data on SDOUT

ADC_DIF[1:0]

00

Left-Justified, 24-bit data

01

I²S, 24-bit data

10

Reserved

11

Reserved

ADC Serial Audio Interface Format

6.7 DAC1 Clocking (Address 07h)

7

Reserved

6

DAC1_MCLK

5

Reserved

4

DAC1_SP

3

Reserved

2

Reserved

1

0

DAC1_DIF1 DAC1_DIF0

6.7.1

DAC1 MCLK Source

This bit selects which MCLK pin provides the clock for DAC1.

DAC1_MCLK

0

1

MCLK1

MCLK2

DAC1 MCLK source

6.7.2

DAC1 Serial Port Source

This bit selects which serial port provides the sub clocks for the DAC1.

DAC1_SP

0

1

Serial Port 1 (SCLK1/LRCK1)

Serial Port 2 (SCLK2/LRCK2)

DAC1 sub clock source

6.7.3

DAC1 Digital Interface Format (DAC1_DIF)

These bits configure the serial audio interface format for incoming digital audio data on SDIN1.

DAC1_DIF[1:0]

00

01

10

11

DAC1 Serial Audio Interface Format

Left-Justified, up to 24-bit data

I²S, up to 24-bit data

Right Justified, 16-bit data

Right Justified, 24-bit data

DS721A6

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