CS42888-DQZR 데이터 시트보기 (PDF) - Cirrus Logic

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CS42888-DQZR

108 dB, 192 kHz 4-In, 8-Out CODEC

Cirrus Logic 

CS42888

Notes:

16. After powering up the CS42888, RST should be held low after the power supplies and clocks are settled.

17. See Table 10 on page 42 and Table 11 on page 43 for suggested MCLK frequencies.

18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only.

19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified

and Time Division Multiplexed interface formats only.

20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively.

LRCK

tlcks

SCLK

DAC_SDINx

ADC_SDOUTx

tds

tdh

MSB

tdpd

MSB

MSB-1

MSB-1

Figure 6. Serial Audio Interface Master Mode Timing

DS717F1

19

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