CS4365-CQZ(2005) 데이터 시트보기 (PDF) - Cirrus Logic
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CS4365-CQZ Datasheet PDF : 51 Pages
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CS4365
DIF3
0
0
0
0
0
0
1
1
1
1
1
X
DIF2
0
0
0
0
1
1
0
0
0
0
1
X
DIF1
0
0
1
1
0
0
0
0
1
1
0
X
DIF0
0
1
0
1
0
1
0
1
0
1
0
X
DESCRIPTION
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
One-line Mode 1, 24-bit Data
One-line Mode 2, 20-bit Data
Reserved
Reserved
TDM
All other combinations are Reserved
Table 7. Digital Interface Formats - PCM Mode
Format
0
1
2
3
4
5
8
9
FIGURE
9
10
11
12
13
14
15
16
12
17
5.3.2 Functional Mode (FM)
Default = 11
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or Auto Speed Mode.
5.4 DSD Control (address 04h)
7
6
5
DSD_DIF2 DSD_DIF1 DSD_DIF0
0
0
0
4
3
2
1
0
DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN
0
1
1
0
0
5.4.1 DSD Mode Digital Interface Format (DSD_dif)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD mode is selected.
DIF2
0
0
0
0
DIF1
0
0
1
1
DIFO
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
Table 8. Digital Interface Formats - DSD Mode
36
DS670PP1
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