CRD44800-ST-FB 데이터 시트보기 (PDF) - Cirrus Logic
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CRD44800-ST-FB Datasheet PDF : 76 Pages
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CS44600
SWITCHING CHARACTERISTICS - DAI INTERFACE
(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)
Parameters
Symbol
Min
RST pin Low Pulse Width
(Note 15)
1
DAI_MCLK Duty Cycle
(Note 16)
40
DAI_SCLK Duty Cycle
45
DAI_LRCK Duty Cycle
45
DAI Sample Rate
(Note 17) Fs
32
DAI_SDIN Setup Time Before DAI_SCLK Rising Edge
tds
10
DAI_SDIN Hold Time After DAI_SCLK Rising Edge
tdh
10
DAI_SCLK High Time
tsckh
20
DAI_SCLK Low Time
tsckl
20
DAI_LRCK Setup Time Before DAI_SCLK Rising Edge
tlrcks
25
DAI_SCLK Rising Edge Before DAI_LRCK Edge
tlrckd
25
Max
-
60
55
55
192
-
-
-
-
-
-
Units
ms
%
%
%
kHz
ns
ns
ns
ns
ns
ns
15. After powering up, the CS44600, RST should be held low until after the power supplies and clocks are set-
tled.
16. See Table 1 on page 26 for suggested MCLK frequencies.
17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.
D A I_ L R C K
DAI_SC LK
t lrckd
t lrcks
t sckh
tsckl
D AI_SD IN x
t ds
t dh
Figure 6. Serial Audio Interface Timing
DAI_LRCK
(input)
t lrcks
t lrckd
DAI_SCLK
(input)
DAI_SDIN1
t lrcks
t sckh
tds
tdh
MSB
tsckl
MSB-1
Figure 7. Serial Audio Interface Timing - TDM Mode
DS633F1
13
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