CS4955-CQZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS4955-CQZ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

must be tied to ground. PDAT [7:0] are available to mode. For 3.3 V operation it is necessary to have

be used for GPIO operation in I²C host interface the appropriate level shifting for I²C signals.

SDA

SCL

A

Start

1-7

8

Address R/W

9

ACK

1-7 8 9

Data ACK

1-7

8

9

Data ACK

P

Stop

Note: I²C transfers data always with MSB first, LSB last

Figure 26. I²C Protocol

8.1.2 8-bit Parallel Interface

The CS4954/5 is equipped with a full 8-bit parallel

microprocessor write and read control port. Along

with the PDAT [7:0] pins, the control port interface

is comprised of host read (RD) and host write (WR)

active low strobes and host address enable

(ADDR), which, when low, enables unique address

register accesses. The control port is used to access

internal registers which configure the CS4954/5 for

various modes of operation. The internal registers

are uniquely addressed via an address register. The

address register is accessed during a host write cy-

cle when the WR and ADDR pins set low. Host

write cycles with ADDR set high will write 8-bit

data to the PDAT [7:0] pins into the register cur-

rently selected by the address register. Likewise

read cycles occuring with RD set low and ADDR

set high will return the register contents selected by

the address register. Reference the detailed electri-

cal timing parameter section of this data sheet for

exact host parallel interface timing characteristics

and specifications.

WR

Trec

Trec

RD

Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle

DS278F6

35

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