CS5368(2005) 데이터 시트보기 (PDF) - Cirrus Logic
부품명
상세내역
제조사
CS5368 Datasheet PDF : 39 Pages
| |||
CS5368
4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format
The format of the data at the Serial Audio Interface ports is controlled by the settings of the DIF1 and DIF0
pins in standalone mode, or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control-
Port Mode.
.
DIF1
0
0
1
1
DIF0
0
1
0
1
Mode
Left Justified
I²S
TDM (2 wire)
TDM (4 wire)
Table 3. DIF1 and DIF0 Pin Settings
4.6.7 Master Mode Audio Clocking
Figure 11. "Master Mode Clock Dividers" shows the configuration of the MCLK dividers and the sample
rate dividers while in Master Mode.
S A M P L E R A T E D IV ID E R S
MCLK
M C L K D IV ID E R S
0 /1
0 /1
÷1
÷1
÷ 1 .5
÷2
0 /1
÷1
÷2
p in C M O D E
M D IV
b it C M O D E M D IV 1
n /a
M D IV 0
÷ 256
S in g le
Speed
00
÷ 128
D o u b le
Speed
01
÷ 64
Quad
10
Speed
M1 M0
÷4
÷2
÷1
S in g le
Speed
00
D o u b le
Speed
01
Quad
Speed
10
LRCK/ FS
SCLK
Figure 11. Master Mode Clock Dividers
4.6.8 Slave Mode Audio Clocking
In Slave Mode, the sampling rate is auto-set by examining the incoming MCLK and LRCK/FS signals.
LRCK/FS and SCLK operate as inputs in Slave Mode. It is recommended that the LRCK/FS be synchro-
nously derived from the Master clock, and it must be equal to the desired sampling rate, Fs.
28
DS624A1
Share Link: 