CS5378 데이터 시트보기 (PDF) - Cirrus Logic

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CS5378

Low-power Single-channel Decimation Filter

Cirrus Logic 

CS5378

6.4 Master Clock Jitter and Skew

Care must be taken to minimize jitter and skew on

the distributed system clock as both parameters af-

fect measurement performance.

Jitter on the input clock causes jitter in the generat-

ed modulator clock, resulting in sample timing er-

rors and increased noise.

Skew between input clocks from node to node cre-

ates a sample timing offset, resulting in systematic

measurement errors in a reconstructed signal.

DS639F2

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