DSPIC30F1013AT-30E/ML 데이터 시트보기 (PDF) - Microchip Technology
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DSPIC30F1013AT-30E/ML Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
The following figure depicts the recommended circuit
for the conversion rates above 200 ksps. The
dsPIC30F3014 is shown as an example.
FIGURE 19-2:
ADC VOLTAGE REFERENCE SCHEMATIC
VDD
VDD
R2
10
C2
0.1 μF
C1
0.01 μF
1
2
3
4
5
6 VSS
7 VDD
8 VDD
9
10
11
dsPIC30F3014
33
32
VSS 31
VSS 30
VDD 29
VDD 28
27
26
25
24
23
R1
VDD
10
See Note 1:
VDD
VDD
VDD
C8
C7
C6
1 μF
0.1 μF 0.01 μF
VDD
AVDD
AVDD
AVDD
C5
C4
C3
1 μF
0.1 μF 0.01 μF
Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
19.7.1 200 KSPS CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 19-2.
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 19-2.
• Set SSRC<2.0> = 111 in the ADCON1 register to
enable the auto-convert option.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3.0> control bits in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the ADC clock period to be:
1
= 334 ns
(14 + 1) x 200,000
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 TAD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The TAD selection in conjunc-
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 19-1 for code
example.
© 2007 Microchip Technology Inc.
DS70138E-page 129
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