JS28F320J3C-115 데이터 시트보기 (PDF) - Intel

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JS28F320J3C-115

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

Table 18. Status Register Definitions

WSMS

bit 7

High Z

When

Busy?

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

ESS

bit 6

ECLBS

bit 5

PSLBS

bit 4

VPENS

bit 3

PSS

bit2

DPS

bit 1

R

bit 0

Status Register Bits

Notes

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

SR.6 = ERASE SUSPEND STATUS

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS

1 = Error in Block Erasure or Clear Lock-Bits

0 = Successful Block Erase or Clear Lock-Bits

SR.4 = PROGRAM AND SET LOCK-BIT STATUS

1 = Program Error / Error in Setting Lock-Bit

0 = Successful Program/Set Block Lock Bit

SR.3 = PROGRAMMING VOLTAGE STATUS

1 = Low Programming Voltage Detected, Operation

Aborted

0 = Programming Voltage OK

SR.2 = PROGRAM SUSPEND STATUS

1 = Program suspended

0 = Program in progress/completed

SR.1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit Detected, Operation Abort

0 = Unlock

SR0 = RESERVED FOR FUTURE ENHANCEMENTS

Check STS or SR.7 to determine block erase,

program, or lock-bit configuration completion.

SR[6:0] are not driven while SR.7 = “0.”

If both SR.5 and SR.4 are “1”s after a block erase or

lock-bit configuration attempt, an improper

command sequence was entered.

SR.3 does not provide a continuous programming

voltage level indication. The WSM interrogates and

indicates the programming voltage level only after

Block Erase, Program, Set Block Lock-Bit, or Clear

Block Lock-Bits command sequences.

SR.1 does not provide a continuous indication of

block lock-bit values. The WSM interrogates the

block lock-bits only after Block Erase, Program, or

Lock-Bit configuration command sequences. It

informs the system, depending on the attempted

operation, if the block lock-bit is set. Read the block

lock configuration codes using the Read Identifier

Codes command to determine block lock-bit status.

SR0 is reserved for future use and should be

masked when polling the Status Register.

Table 19. Extended Status Register Definitions

WBS

Reserved

bit 7

Bits 6 -- 0

High Z

When

Busy?

No

Yes

Status Register Bits

XSR.7 = WRITE BUFFER STATUS

1 = Write buffer available

0 = Write buffer not available

XSR.6–XSR0 = RESERVED FOR FUTURE

ENHANCEMENTS

Notes

After a Buffer-Write command, XSR.7 = 1 indicates

that a Write Buffer is available.

SR[6:0] are reserved for future use and should be

masked when polling the Status Register.

40

Datasheet

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