JS28F320J3C-115 데이터 시트보기 (PDF) - Intel
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JS28F320J3C-115 Datasheet PDF : 72 Pages
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256-Mbit J3 (x8/x16)
Figure 26. Protection Register Programming Flowchart
Start
Write C0H
(Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read Status Register
No
SR.7 = 1?
Yes
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1, 1
SR.3, SR.4 =
VPEN Range Error
0,1
SR.1, SR.4 =
Protection Register
Programming Error
SR.1, SR.4 =
1,1 Attempted Program to
Locked Register -
Aborted
Program Successful
Bus Operation
Command
Comments
Write
Write
Read
Standby
Protection Program
Setup
Data = C0H
Protection Program
Data = Data to Program
Addr = Location to Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Command
Comments
Standby
Standby
SR.1 SR.3 SR.4
0
1 1 V PEN Low
0 0 1 Prot. Reg.
Prog. Error
Standby
1 0 1 Register
Locked:
Aborted
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
Datasheet
67
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