DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PIC16LF627A-I/ML 데이터 시트보기 (PDF) - Microchip Technology

부품명
상세내역
제조사
PIC16LF627A-I/ML Datasheet PDF : 178 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
PIC16F627A/628A/648A
6.3 Timer0 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.
FIGURE 6-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT
Data Bus
T0CKI
pin
0
1
T0SE
T0CS
TMR1 Clock Source
1
0
PSA
SYNC
2
Cycles
8
TMR0 Reg
Set flag bit T0IF
on Overflow
Watchdog
Timer
WDT Enable bit
0
1
PSA
WDT Postscaler/
TMR0 Prescaler
8
8-to-1MUX
PS<2:0>
1
WDT
0
Time-out
PSA
Note: T0SE, T0CS, PSA., PS<2:0> are bits in the Option Register.
DS40044F-page 46
© 2007 Microchip Technology Inc.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]