PIC16LCR67-04/P 데이터 시트보기 (PDF) - Microchip Technology

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PIC16LCR67-04/P

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 22-11: I2C BUS DATA TIMING

103

100

102

101

SCL

90

106

107

91

SDA

In

109

109

92

110

SDA

Out

Note: Refer to Figure 22-1 for load conditions

TABLE 22-10: I2C BUS DATA REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Max Units

Conditions

100*

THIGH Clock high time

100 kHz mode

4.0

—

µs Device must operate at a min-

imum of 1.5 MHz

400 kHz mode

0.6

—

µs Device must operate at a min-

imum of 10 MHz

SSP Module

1.5TCY

—

101*

TLOW Clock low time

100 kHz mode

4.7

—

µs Device must operate at a min-

imum of 1.5 MHz

400 kHz mode

1.3

—

µs Device must operate at a min-

imum of 10 MHz

SSP Module

1.5TCY

—

102*

TR SDA and SCL rise

100 kHz mode

—

1000 ns

time

400 kHz mode 20 + 0.1Cb 300

ns Cb is specified to be from

10-400 pF

103*

TF SDA and SCL fall time 100 kHz mode

—

300

ns

400 kHz mode 20 + 0.1Cb 300

ns Cb is specified to be from

10-400 pF

90*

TSU:STA START condition

setup time

100 kHz mode

400 kHz mode

4.7

—

µs Only relevant for repeated

0.6

—

µs START condition

91*

THD:STA START condition hold 100 kHz mode

time

400 kHz mode

4.0

—

µs After this period the first clock

0.6

—

µs pulse is generated

106*

THD:DAT Data input hold time 100 kHz mode

0

—

ns

400 kHz mode

0

0.9

µs

107*

TSU:DAT Data input setup time 100 kHz mode

250

—

ns Note 2

400 kHz mode

100

—

ns

92*

TSU:STO STOP condition setup 100 kHz mode

time

400 kHz mode

4.7

—

µs

0.6

—

µs

109*

TAA Output valid from

100 kHz mode

—

3500 ns Note 1

clock

400 kHz mode

—

—

ns

110*

TBUF Bus free time

100 kHz mode

400 kHz mode

4.7

—

µs Time the bus must be free

1.3

—

µs before a new transmission can

start

Cb Bus capacitive loading

—

400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement

Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is

released.

© 1997 Microchip Technology Inc.

Preliminary

DS30234D-page 261

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