PIC16LCR63T-20/JW 데이터 시트보기 (PDF) - Microchip Technology

부품명

상세내역

제조사

PIC16LCR63T-20/JW

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch)

R/W-0

—

bit7

R/W-0

—

R-0

RCIF

R-0

TXIF

R/W-0

SSPIF

R/W-0

CCP1IF

R/W-0

TMR2IF

R/W-0

TMR1IF

bit0

bit 7-6: Reserved: Always maintain these bits clear.

bit 5:

RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty

bit 4:

TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full

bit 3:

SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register overflow occurred

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to

enabling an interrupt.

DS30234D-page 42

© 1997 Microchip Technology Inc.

Share Link: