PIC16C711-04ISO 데이터 시트보기 (PDF) - Microchip Technology
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PIC16C711-04ISO Datasheet PDF : 176 Pages
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PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 15-6: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK 132
A/D DATA
ADRES
ADIF
GO
SAMPLE
(TOSC/2) (1)
1 Tcy
131
130
7
6
5
4
3
2
1
0
OLD_DATA
NEW_DATA
SAMPLING STOPPED
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 15-7: A/D CONVERSION REQUIREMENTS
Param
No.
130
131
132
Sym
TAD
TCNV
TACQ
Characteristic
A/D clock period
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
Conversion time
(not including S/H time) (Note 1)
Acquisition time
Min
Typ† Max Units
Conditions
2.0
—
—
µs TOSC based, VREF ≥ 3.0V
2.0
—
—
µs TOSC based, VREF full range
2.0
4.0
6.0
µs A/D RC Mode
3.0
6.0
9.0
µs A/D RC Mode
—
9.5
—
TAD
Note 2 20
—
µs
5*
—
—
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than
1 LSb (i.e., 19.5 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134 TGO Q4 to A/D clock start
— Tosc/2§ —
— If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time
1.5§
—
—
TAD
*
†
§
Note 1:
2:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These specifications ensured by design.
ADRES register may be read on the following TCY cycle.
See Section 7.1 for min conditions.
DS30272A-page 146
© 1997 Microchip Technology Inc.
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