PIC18F45J50-I/SOSQTP 데이터 시트보기 (PDF) - Microchip Technology
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PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
11.4 Application Examples
This section introduces some potential applications for
the PMP module.
11.4.1
MULTIPLEXED MEMORY OR
PERIPHERAL
Figure 11-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
FIGURE 11-27: MULTIPLEXED ADDRESSING APPLICATION EXAMPLE
PIC18F
PMD<7:0>
PMALL
PMALH
PMCS
PMRD
PMWR
373 A<7:0>
D<7:0>
A<15:8>
373
A<13:0>
D<7:0>
CE
OE WR
Address Bus
Data Bus
Control Lines
11.4.2
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 provides an example of a
memory or peripheral that is partially multiplexed with
an external latch. If the peripheral has internal latches,
as displayed in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
PMALL
PMCS
PMRD
PMWR
373 A<7:0>
D<7:0>
A<7:0>
D<7:0>
CE
OE WR
Address Bus
Data Bus
Control Lines
FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC18F
PMD<7:0>
PMALL
PMCS
PMRD
PMWR
Parallel Peripheral
AD<7:0>
ALE
CS
RD
WR
Address Bus
Data Bus
Control Lines
2011 Microchip Technology Inc.
DS39931D-page 191
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