PIC18F44J50-I/SPSQTP 데이터 시트보기 (PDF) - Microchip Technology
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PIC18F44J50-I/SPSQTP
Microchip Technology
PIC18F44J50-I/SPSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h)
bit 0
ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1:
2:
3:
4:
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return random values.
For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10 ms
before performing a conversion on this channel.
On package types that have AVDD and AVSS pins, these pins should be externally connected to VDD and
VSS levels at the circuit board level. Package types that do not have AVDD and AVSS pins, tie AVDD and
AVSS to VDD and VSS internally.
REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h)
R/W-0
ADFM
bit 7
R/W-0
ADCAL
R/W-0
ACQT2
R/W-0
ACQT1
R/W-0
ACQT0
R/W-0
ADCS2
R/W-0
ADCS1
R/W-0
ADCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-3
bit 2-0
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D Converter operation
ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD
ADCS<2:0>: A/D Conversion Clock Select bits
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
DS39931D-page 348
2011 Microchip Technology Inc.
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