PIC18F45J50-I/SOSQTP 데이터 시트보기 (PDF) - Microchip Technology
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PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
REGISTER 22-2: UCFG: USB CONFIGURATION REGISTER (BANKED F39h)
R/W-0
UTEYE
bit 7
R/W-0
UOEMON
U-0
R/W-0
R/W-0
R/W-0
—
UPUEN(1,2) UTRDIS(1,3) FSEN(1)
R/W-0
PPB1
R/W-0
PPB0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test is enabled
0 = Eye pattern test is disabled
UOEMON: USB OE Monitor Enable bit
1 = UOE signal is active, indicating intervals during which the D+/D- lines are driving
0 = UOE signal is inactive
Unimplemented: Read as ‘0’
UPUEN: USB On-Chip Pull-up Enable bit(1,2)
1 = On-chip pull-up is enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up is disabled
UTRDIS: On-Chip Transceiver Disable bit(1,3)
1 = On-chip transceiver is disabled
0 = On-chip transceiver is active
FSEN: Full-Speed Enable bit(1)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers are enabled for all endpoints
01 = Even/Odd ping-pong buffer are enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers are disabled
Note 1:
2:
3:
The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
If UTRDIS is set, the UOE signal will be active, independent of the UOEMON bit setting.
2011 Microchip Technology Inc.
DS39931D-page 361
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