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PIC18F45J50-I/SOSQTP 데이터 시트보기 (PDF) - Microchip Technology

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PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
POR and BOR, MCLR and WDT Resets and WDT
wake-ups.
TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1) CM
RCON Register
STKPTR Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESET instruction
0000h
1
1
1
1
0
0
0
0
0000h
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
1
u
0
u
u
Configuration Mismatch Reset
0000h
0
u
u
u
u
u
u
u
MCLR Reset during
0000h
u
u
1
u
u
u
u
u
power-managed Run modes
MCLR Reset during
0000h
u
u
1
0
u
u
u
u
power-managed Idle modes and
Sleep mode
MCLR Reset during full-power
0000h
u
u
u
u
u
u
u
u
execution
Stack Full Reset (STVREN = 1) 0000h
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
0000h
u
u
u
u
u
u
u
1
actual Reset, STVREN = 0)
WDT time-out during full-power 0000h
u
u
0
u
u
u
u
u
or power-managed Run modes
WDT time-out during
PC + 2
u
u
0
0
u
u
u
u
power-managed Idle or Sleep
modes
Interrupt exit from
power-managed modes
PC + 2
u
u
u
0
u
u
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39931D-page 68
2011 Microchip Technology Inc.

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