PSD511B1-C-90UI 데이터 시트보기 (PDF) - STMicroelectronics
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PSD511B1-C-90UI Datasheet PDF : 153 Pages
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PSD5XX Family
AC/DC Parameters – ZPLD Timing Parameters
(ZPSD5XXV Versions)
Asynchronous Clock Mode (3.0 V ± 10%, Note 1)
Symbol
Parameter
Conditions
-20
Min Max
-25
Min Max
ZPLD_TURBO
OFF*
f MAXA
t SA
t HA
t CHA
t CLA
t COA
t ARD
t MINA
Maximum Frequency
External Feedback
1/(tSA + tCOA)
Maximum Frequency
1/(tS A+ tCO A–10)
Internal Feedback (fCNTA) (Note 1)
Maximum Frequency
Pipelined Data
1/(tCH + tCL)
Input Setup Time
Any Input
Input Hold Time
Any Input
Clock High Time
Any Input
Clock Low Time
Any Input
Clock to Output Delay
Any Input to Port B
Array Delay for Product
Term Expansion
Any Macrocell
Minimum Clock Period 1/fCNT
14.49
11.11
16.95
12.50
31.25
18.52
13
30
13
30
25
27
16
27
56
60
33
35
59
80
Add 20
0
0
0
Add 20
0
0
NOTE: 1. Only Port B has asynchronous outputs. Clock into macrocell Flip Flop is generated by a product term.
*NOTE: If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
122
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