PSD802G2-C-20UI 데이터 시트보기 (PDF) - STMicroelectronics
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PSD802G2-C-20UI Datasheet PDF : 110 Pages
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PSD835G2
PSD8XX Family
Microcontroller Interface – PSD835G2 AC/DC Parameters
(5V ± 10% Versions)
Port F Peripheral Data Mode Read Timing (5 V ± 10%)
Symbol
t AVQV (PF)
t SLQV (PF)
t RLQV (PF)
t DVQV (PF)
t QXRH (PF)
t RLRH (PF)
t RHQZ (PF)
Parameter
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
Conditions
(Note 3)
(Notes 1 and 4)
(Note 1)
(Note 1)
-70
Min Max
30
25
21
31
22
0
27
23
-90
Turbo
Min Max Off Unit
35 Add 12 ns
35 Add 12 ns
32
ns
38
ns
30
ns
0
ns
32
ns
25
ns
Port F Peripheral Data Mode Write Timing (5 V ± 10%)
Symbol
Parameter
t WLQV (PF)
t DVQV (PF)
t WHQZ (PF)
WR to Data Propagation Delay
Data to Port F Data Propagation Delay
WR Invalid to Port F Tri-state
NOTES: 1.
2.
3.
4.
5.
RD timing has the same timing as DS and PSEN signals.
WR timing has the same timing as E and DS signals.
Any input used to select Port F Data Peripheral Mode.
Data is already stable on Port F.
Data stable on ADIO pins to data on Port F.
Conditions
(Note 2)
(Note 5)
(Note 2)
-70
-90
Min Max Min Max Unit
25
35 ns
22
30 ns
20
25 ns
83
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