PSD933312MIT 데이터 시트보기 (PDF) - STMicroelectronics
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PSD933312MIT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 45. DC Characteristics (5V devices)
Symbol
Parameter
Test Condition
(in addition to those in
Table 39., page 76)
Min.
Typ.
Max.
Unit
VIH
Input High Voltage
4.5 V < VCC < 5.5 V
2
VCC +0.5
V
VIL
Input Low Voltage
4.5 V < VCC < 5.5 V
–0.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
0.8VCC
VCC +0.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–0.5
0.2VCC –0.1 V
VHYS
Reset Pin Hysteresis
0.3
V
VLKO
VCC (min) for Flash Erase and
Program
2.5
4.2
V
VOL
Output Low Voltage
IOL = 20µA, VCC = 4.5 V
IOL = 8mA, VCC = 4.5 V
0.01
0.1
V
0.25
0.45
V
VOH
Output High Voltage Except
VSTBY On
IOH = –20µA, VCC = 4.5 V
IOH = –2mA, VCC = 4.5 V
4.4
2.4
4.49
3.9
V
V
VOH1
Output High Voltage VSTBY On
IOH1 = 1µA
VSTBY – 0.8
V
VSTBY SRAM Stand-by Voltage
2.0
VCC
V
ISTBY
SRAM Stand-by Current
VCC = 0 V
0.5
1
µA
IIDLE
Idle Current (VSTBY input)
VCC > VSTBY
–0.1
0.1
µA
VDF
SRAM Data Retention Voltage
Only on VSTBY
2
V
ISB
Stand-by Supply Current
for Power-down Mode
CSI >VCC –0.3 V (Notes 2,3)
50
200
µA
ILI
Input Leakage Current
VSS < VIN < VCC
–1
±0.1
1
µA
ILO
Output Leakage Current
0.45 < VOUT < VCC
–10
±5
10
µA
ICC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
Flash memory
PLD_TURBO = Off,
f = 0 MHz (Note 5)
PLD_TURBO = On,
f = 0 MHz
During Flash memory
WRITE/Erase Only
Read only, f = 0 MHz
0
µA/PT
400
700
µA/PT
15
30
mA
0
0
mA
SRAM
f = 0 MHz
0
0
mA
PLD AC Adder
note 4
ICC (AC) Flash memory AC Adder
(Note 5)
SRAM AC Adder
2.5
3.5
mA/
MHz
1.5
3.0
mA/
MHz
Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 35., page 72 for the PLD current calculation.
5. IOUT = 0mA
78/110
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