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ST72521AR9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

MCCSR Power Saving Mode entered when HALT

OIE bit

instruction is executed

0 HALT mode

1 ACTIVE-HALT mode

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set (see Section

10.2 on page 58 for more details on the MCCSR

register).

The MCU can exit ACTIVE-HALT mode on recep-

tion of an MCC/RTC interrupt or a RESET. When

exiting ACTIVE-HALT mode by means of an MCC/

RTC interrupt, no 256 or 4096 CPU cycle delay oc-

curs. The CPU resumes operation by servicing the

interrupt or by fetching the reset vector which

woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are forced to ‘10b’ to enable in-

terrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE-HALT mode while the Watchdog

is active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode fol-

lowing an MCC/RTC interrupt, OIE bit of MCCSR

register must not be cleared before tDELAY after

the interrupt occurs (tDELAY = 256 or 4096 tCPU de-

lay depending on option byte). Otherwise, the ST7

enters HALT mode for the remaining tDELAY peri-

od.

Figure 26. ACTIVE-HALT Timing Overview

ACTIVE 256 OR 4096 CPU

RUN HALT CYCLE DELAY 1)

RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

RESET

OR

INTERRUPT

FETCH

VECTOR

Figure 27. ACTIVE-HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=1)

OSCILLATOR

PERIPHERALS 2)

CPU

I[1:0] BITS

ON

OFF

OFF

10

N

RESET

N

Y

INTERRUPT 3)

OSCILLATOR

ON

Y

PERIPHERALS

OFF

CPU

ON

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

ON

ON

XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source

can still be active.

3. Only the MCC/RTC interrupt can exit the MCU

from ACTIVE-HALT mode.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

register is popped.

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