ST7MC2N6 데이터 시트보기 (PDF) - STMicroelectronics

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ST7MC2N6

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

IMPORTANT NOTES (Cont’d)

15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE

INTERRUPT ROUTINE

When an active interrupt request occurs at the

same time as the related flag or interrupt mask is

being cleared, the CC register may be corrupted.

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

- The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

- The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine

- The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request

Ex:

SIM

reset flag or interrupt mask

RIM

15.3 TIMD SET SIMULTANEOUSLY WITH OC

INTERRUPT

If the 16-bit timer is disabled at the same time as

the output compare event occurs then the output

compare flag gets locked and cannot be cleared

before the timer is enabled again.

15.3.1 Impact on the application

If the output compare interrupt is enabled, then the

output compare flag cannot be cleared in the timer

interrupt routine. Consequently the interrupt serv-

ice routine is called repeatedly and the application

gets stuck which causes the watchdog reset if en-

abled by the application.

15.3.2 Workaround

Disable the timer interrupt before disabling the tim-

er. While enabling, first enable the timer, then en-

able the timer interrupts.

Perform the following to disable the timer

– TACR1 or TBCR1 = 0x00h; // Disable the com-

pare interrupt.

– TACSR | or TBCSR |= 0x40; // Disable the timer.

– Perform the following to enable the timer again

– TACSR & or TBCSR & = ~0x40; // Enable the

timer.

– TACR1 or TBCR1 = 0x40; // Enable the compare

interrupt.

Nested interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

- The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

- The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine with high-

er or identical priority level

- The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset flag or interrupt mask

POP CC

15.4 LINSCI LIMITATIONS

15.4.1 LINSCI wrong break duration

SCI Mode

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

cy of 19200 baud (fCPU=8MHz and SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

300/309

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