ST7MC2N6T3 데이터 시트보기 (PDF) - STMicroelectronics
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ST7MC2N6T3
STMicroelectronics
ST7MC2N6T3 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
AD-
STS
ADC
IE
BC1
BC0
Bit 7:4 = Reserved, must be kept cleared.
Bit 3 = ADSTS A/D Converter Sample Time
Stretch
This bit is set and cleared by software to enable or
disable the A/D Converter sample time stretch fea-
ture.
0: AD sample time stretch disabled (for standard
impedance analog inputs)
1 AD sample time stretch enabled (for high imped-
ance analog inputs)
Bit 2 = ADCIE A/D Converter Interrupt Enable
This bit is set and cleared by software to enable or
disable the A/D Converter interrupt.
0: AD Interrupt disabled
1 AD Interrupt enabled
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1 BC0
Beep mode with fOSC2=8MHz
0
0
Off
0
1
1
0
1
1
~2-KHz
~1-KHz
~500-Hz
Output
Beep signal
~50% duty cycle
The beep output signal is available in Active-halt
mode but has to be disabled to reduce the con-
sumption.
Table 5. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
0040h
0040h
002Ch
002Dh
Register
Label
SICSR, page0
Reset Value
SICSR, page1
Reset Value
MCCSR
Reset Value
MCCBCR
Reset Value
7
PAGE
0
PAGE
0
MCO
0
0
6
VDIE
0
0
CP1
0
0
5
4
VDF
0
VCOEN
0
CP0
0
LVDRF
x
LOCK
x
SMS
0
0
0
3
0
PLLEN
0
TB1
0
ADSTS
0
2
CFIE
0
0
TB0
0
ADCIE
0
1
0
CSSD
0
CKSEL
0
OIE
0
BC1
0
WDGRF
x
0
OIF
0
BC0
0
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