STLC2500 데이터 시트보기 (PDF) - STMicroelectronics
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STLC2500 Datasheet PDF : 23 Pages
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STLC2500
Table 22. PCM interface timing
Symbol
tWCH
tWCL
tWSH
tSSC
tSDC
tHCD
tDCD
Description
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
Setup time, PCM_SYNC high to PCM_CLK low
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input valid
Delay time, PCM_CLK high to PCM_A/B output valid
Figure 8. PCM interface timing
t WCL
Min. Typ. Max. Unit
200
ns
200
ns
200
ns
100
ns
100
ns
100
ns
150
ns
PCM_CLK
t WCH
t SSC
PCM_SYNC
t WSH
PCM_A/B in
PCM_A/B out
tSDC tHCD
MSB
MSB-1
MSB-2
MSB-3
t DCD
MSB
MSB-1
MSB-2
MSB-3
8.3 The JTAG interface
The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the boundary scan
of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7
developments tools. It is also used for the industrial test of the device.
8.4 The GPIOs
The STLC2500 has 4 GPIO pins. They are fully programmable via specific HCI commands. They can be
configured as input, output, interrupt with asynchronous or synchronous edge or level detection and/or
wake-up.
Also other functions are multiplexed on the GPIO pins.
The alternative functions are
– WLAN co-existence control
– I2C interface
– PCM synchronization;
– GPIOs
Some functions are mutually exclusive, as per table 23.
19/23
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