DC and AC parameters
STM690A/692A/703/704/802/805/817/818/819
Table 7. DC and AC characteristics (continued)
Sym
Alter-
native
Description
Test condition(1)
Min
Typ
Max Unit
tREC
RST pulse width
Push-button reset input (STM703/704/819)
140
200
280 ms
STM703/704
150
ns
tMLMH tMR MR pulse width
STM819
1
µs
tMLMR tMRD MR to RST output delay
STM703/704
STM819
250 ns
120
ns
MR glitch immunity
STM819
100
ns
MR pull-up resistor
MR = 0 V, VCC = 5 V
45
63
85 kΩ
Watchdog timer (NOT available on STM703/704/819)
tWD Watchdog timeout period
WDI pulse width
Chip-enable gating (STM818 only)
VRST (max) < VCC < 5.5 V
VRST (max) < VCC < 5.5 V
1.12
50
1.60
2.24 s
ns
E to ECON resistance
E to ECON propagation
delay
VCC = VRST (max)
4.5 V < VCC < 5.5 V
40
150 Ω
2
7 ns
Reset to ECON high delay
(Power-down)
15
µs
ECON short circuit current
VCC = 5 V, disable mode,
E = logic high, ECON = 0 V
0.1
0.75
2.0 mA
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for “L” versions; VCC = 4.5 V to 5.5 V for
“M” versions; and VBAT = 2.8 V (except where noted).
2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of
RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC (min).
Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.
3. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST.
8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.
9. For VCC falling.
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