Z8038018FSC 데이터 시트보기 (PDF) - Zilog

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Z8038018FSC

MICROPROCESSOR

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MICROPROCESSOR

Register

Table 7. Effect of a Reset on Z380 CPU and Related I/O Registers

Reset Value

Comments

Program Counter

Stack Pointer

I

R

Select Register

00000000

00000000

000000

00

00000000

A and F Registers

Register Extensions

0000

I/O Bus Control Register 0

00

Interrupt Enable Register

01

Assigned Vector Base Register

00

Trap and Break Register

00

PCz, PC

SPz, SP

Iz, I

Register Bank 0 Selected:

AF, Main Bank, IX, IY

Native Mode

Maskable Interrupts Disabled, in Mode 0

Bus Request Lock-Off

Register Banks 3-0:

A, F, A’, F’ Unaffected

Register Bank 0:

BCz, DEz, HLz, IYz,

BCz’, DEz’, HLz’, IYz’

(All “non-extended” portions unaffected.)

Register Bank 3-1 Unaffected.

IOCLK = BUSCLK/8

/INT0 Enabled

Table 8. Effect of a Reset on On-chip Peripheral Functions

Peripheral Functions

Reset Conditions

Memory Chip Selects and Waits

Lower Memory Chip Select Signal enabled for lowest 1 MBytes

(00000000H-000FFFFFH), with 7 T1, 3 T2, and 7 T3 waits.

Upper Memory Chip Select Signal enabled for highest

16th MBytes (00F00000H - 00FFFFFFH),

with 7 T1, 3 T2, and 7 T3 waits.

Midrange Memory Chip Select Signal and waits disabled.

I/O Waits

External I/O read, write -- 7 waits.

RETI -- 3 waits.

Interrupt daisy chain -- 7 waits.

DRAM Refresh Controller

Disabled

Standby Mode

Disabled

PS010001-0301

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