Z84C90 데이터 시트보기 (PDF) - Zilog
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Z84C90 Datasheet PDF : 56 Pages
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Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
48
• At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal
• During the time period in which CE is active, IORQ is active, and M1 returns to the
inactive state, all of which occur during the rising edge of the clock.
This problem does not exist with the Z80 CPU; however, other CPUs could be affected.
One of the possible workarounds is to add the M1 not active condition to generate a CE
signal.
PS011804-0612
Precautions & Limitations
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