Z8018933FSC 데이터 시트보기 (PDF) - Zilog
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Z8018933FSC Datasheet PDF : 107 Pages
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Zilog
PRELIMINARY
Bit
Upon Reset
R/W
CNTLB1
Addr 03H
MPBT MP /CTS/ PE0 DR SS2 SS1 SS0
PS
Invalid 0
†
0
0
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
† /CTS - Depending on the condition of /CTS pin.
PS - Cleared to 0.
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
General
Divide Ratio
SS, 2, 1, 0
000
001
010
011
100
101
110
111
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
DR = 1 (x64)
Ø ÷ 160
Ø ÷ 640
Ø ÷ 320
Ø ÷ 1280
Ø ÷ 640
Ø ÷ 2560
Ø ÷ 1280
Ø ÷ 5120
Ø ÷ 2560
Ø ÷ 10240
Ø ÷ 5120
Ø ÷ 20480
Ø ÷ 10240
Ø ÷ 40960
External Clock (Frequency < Ø)
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
Ø ÷ 480
Ø ÷ 960
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
Figure 35. ASCI Control Register B (Ch. 1)
DR = 1 (x64)
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
Ø ÷ 61440
Ø ÷ 122880
DS971890301
45
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