STM32F215VGH7V 데이터 시트보기 (PDF) - STMicroelectronics
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STM32F215VGH7V Datasheet PDF : 173 Pages
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Description
STM32F21xxx
Regulator ON
The regulator ON modes are activated by default on LQFP packages. On UFBGA176
package, they are activated by connecting REGOFF to VSS.
VDD minimum value is 1.8 V.
There are three regulator ON modes:
● MR is used in nominal regulation mode (Run)
● LPR is used in Stop mode
● Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF
● Regulator OFF/internal reset ON
On UFBGA176 package, REGOFF must be connected to VDD.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through VCAP_1 and VCAP_2 pins, in addition to VDD.
The following conditions must be respected:
– VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
– If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to
reach 1.8 V, then PA0 should be connected to the NRST pin (see Figure 6).
Otherwise, PA0 should be asserted low externally during POR until VDD reaches
1.8 V (see Figure 7).
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
Figure 6.
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
VDD
PDR=1.8 V
1.2 V
1.08 V
VCAP_1 /VCAP_2
time
PA0 tied to NRST
NRST
time
18 3
1. This figure is valid both whatever the internal reset mode (ON or OFF).
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Doc ID 17050 Rev 8
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