ST7FLITE39F2B6(2005) 데이터 시트보기 (PDF) - STMicroelectronics

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ST7FLITE39F2B6
(Rev.:2005)

8-BIT MCU WITH SINGLE VOLTAGE FLASH, DATA EEPROM, ADC, TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7LITE3

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

13.2.1 Voltage Characteristics

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

Symbol

Ratings

VDD - VSS

VIN

VESD(HBM)

Supply voltage

Input voltage on any pin 1) & 2)

Electrostatic discharge voltage (Human Body Model)

13.2.2 Current Characteristics

Maximum value

Unit

7.0

V

VSS-0.3 to VDD+0.3

see section 13.7.3 on page 143

Symbol

IVDD

IVSS

Ratings

Maximum value

Unit

Total current into VDD power lines (source) 3)

150

Total current out of VSS ground lines (sink) 3)

150

Output current sunk by any standard I/O and control pin

25

IIO

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

Injected current on RESET pin

50

-25

mA

±5

IINJ(PIN) 2) & 4)

Injected current on OSC1 and OSC2 pins

Injected current on PB0 and PB1 pins 5)

±5

+5

Injected current on any other pin 6)

±5

ΣIINJ(PIN) 2)

Total injected current (sum of all I/O and control pins) 6)

±20

13.2.3 Thermal Characteristics

Symbol

Ratings

Value

Unit

TSTG

Storage temperature range

-65 to +150

°C

TJ

Maximum junction temperature (see section 14.2 on page 156)

Notes:

1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.

2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the

corresponding VIN maximum must always be respected

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout

the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage

is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as

far as possible from the analog input pins.

5. No negative current injection allowed on PB0 and PB1 pins.

6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-

mum current injection on four I/O port pins of the device.

130/167

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