LFSC3GA25E-5FN900I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFSC3GA25E-5FN900I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

LatticeSC/M sysCONFIG Port Timing

Over Recommended Operating Conditions

Parameter

Description

General Configuration Timing

tSMODE

tHMODE

M[3:0] Setup Time to INITN High

M[3:0] Hold Time from INITN High

tRW

RESETN Pulse Width Low to Start Reconfiguration (1.2 V)

tPGW

PROGRAMN Pulse Width Low to Start Reconfiguration (1.2 V)

fESB_CLK_FRQ

System Bus ESB_CLK Frequency (No Wait States)

sysCONFIG Master Parallel Configuration Mode

tSMB

tHMB

D[7:0] Setup Time to RCLK High

D[7:0] Hold Time to RCLK High

tCLMB

RCLK Low Time (Non-compressed Bitstreams)

RCLK Low Time (Compressed Bitstreams)

tCHMB

RCLK High Time

sysCONFIG SPI Port

tCFGX

tCSSPI

tSCK

tSOCDO

tCSPID

fMAXSPI

INITN High to CSCK Low

INITN High to CSSPIN Low

CSCK Low before CSSPIN Low

CSCK Low to Output Valid

CSSPIN Low to CSCK high Setup Time

Max CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)

(SPIFASTN=0)

tSUSPI

tHSPI

SOSPI/D0 Data Setup Time Before CSCK

SOSPI/D0 Data Hold Time After CSCK

Master Clock Frequency

Duty Cycle

sysCONFIG Master Serial Configuration Mode

tSMS

DIN Setup Time

tHMS

DIN Hold Time

fCMS

CCLK Frequency (No Divider)

fC_DIV

CCLK Frequency (Div 128)

tD

CCLK to DOUT Delay

sysCONFIG Master Parallel Configuration Mode

tAVMP

tSMP

tHMP

tCLMP

RCLK to Address Valid

D[7:0] Setup Time to RCLK High

D[7:0] Hold Time to RCLK High

RCLK Low Time (Non-compressed Bitstream)

RCLK Low Time (Compressed Bitstream)

tCHMP

tDMP

RCLK High Time

CCLK to DOUT

Min.

Max.

Units

0

—

600

—

50 (or 100 at

0.95V)

—

50 (or 100 at

0.95V)

—

—

133

ns

ns

ns

ns

MHz

6

—

ns

0

—

ns

0.5

0.5

CCLK

periods

0.5

7.5

CCLK

periods

0.5

0.5

CCLK

periods

—

80

0

2

0

—

—

15

—

15

—

50

7

2

Selected

value - 30%

40

—

—

Selected

value + 30%

60

ns

µs

ns

ns

ns

MHz

ns

ns

MHz

%

4.4

—

ns

0

—

ns

90

190

MHz

0.70

1.48

MHz

—

7.5

ns

—

10

ns

6

—

ns

0

—

ns

7.5

7.5

CCLK

0.5

63.5

periods

0.5

0.5

CCLK

periods

—

7.5

ns

3-27

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