Electrical characteristics
STM32F091xB STM32F091xC
Table 60. DAC characteristics (continued)
Symbol
Parameter
Min Typ
Max
Unit
Comments
Gain error(3) Gain error
-
-
±0.5
%
Given for the DAC in 12-bit
configuration
Settling time (full scale: for a
10-bit input code transition
tSETTLING(3)
between the lowest and the
highest input codes when
-
3
DAC_OUT reaches final
value ±1LSB
4
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
Update
rate(3)
DAC_OUT change when
small variation in the input
-
-
code (from code i to i+1LSB)
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
-
6.5
10
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
µs input code between lowest and
DAC Control register)
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
- –67
–40
dB No RLOAD, CLOAD = 50 pF
measurement
1. Guaranteed by design, not tested in production.
2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.
3. Data based on characterization results, not tested in production.
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