R5F10366DSP-V0 데이터 시트보기 (PDF) - Renesas Electronics

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R5F10366DSP-V0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)

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5. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.

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6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V

Maximum transfer rate =

1

{−Cb × Rb × ln (1 −

2.0

Vb

)} × 3

[bps]

Baud rate error (theoretical value) =

1

Transfer rate × 2

− {−Cb × Rb × ln (1 −

2.0

Vb

)}

(

1

Transfer

rate

)

×

Number

of

transferred

bits

× 100 [%]

* This value is the theoretical value of the relative difference between the transmission and reception sides.

<R>

7. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

<R>

8. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

Maximum transfer rate =

1

{−Cb × Rb × ln (1 −

1.5

Vb

)} × 3

[bps]

Baud rate error (theoretical value) =

1

Transfer rate × 2

− {−Cb × Rb × ln (1 −

1.5

Vb

)}

(

1

Transfer

rate

)

×

Number

of

transferred

bits

× 100 [%]

* This value is the theoretical value of the relative difference between the transmission and reception sides.

<R>

9. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer.

Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for

the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).

For VIH and VIL, see the DC characteristics with TTL input buffer selected.

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 39 of 106

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