DSPIC33FJ128GPX04 데이터 시트보기 (PDF) - Microchip Technology

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DSPIC33FJ128GPX04

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

TABLE 4-10: UART2 REGISTER MAP

SFR Name

SFR

Addr

Bit 15

Bit 14 Bit 13

Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

U2MODE

U2STA

U2TXREG

U2RXREG

U2BRG

Legend:

0230 UARTEN

—

USIDL IREN RTSMD

—

UEN1 UEN0 WAKE LPBACK

0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT

URXISEL<1:0>

0234

—

—

—

—

—

—

—

UTX8

0236

—

—

—

—

—

—

—

URX8

0238

Baud Rate Generator Prescaler

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 5

Bit 4

Bit 3

ABAUD URXINV BRGH

ADDEN RIDLE PERR

UART Transmit Register

UART Receive Register

Bit 2

Bit 1

PDSEL<1:0>

FERR OERR

Bit 0

STSEL

URXDA

All

Resets

0000

0110

xxxx

0000

0000

TABLE 4-11: SPI1 REGISTER MAP

SFR Name

SFR

Addr

Bit 15

Bit 14

Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

SPI1STAT

SPI1CON1

SPI1CON2

SPI1BUF

Legend:

0240 SPIEN

—

SPISIDL —

—

—

—

—

—

SPIROV

0242

—

—

—

DISSCK DISSDO MODE16 SMP

CKE

SSEN

CKP

0244 FRMEN SPIFSD FRMPOL —

—

—

—

—

—

—

0248

SPI1 Transmit and Receive Buffer Register

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

—

MSTEN

—

Bit 4

Bit 3

Bit 2

—

—

—

SPRE<2:0>

—

—

—

Bit 1

Bit 0

All

Resets

SPITBF SPIRBF

PPRE<1:0>

FRMDLY —

0000

0000

0000

0000

TABLE 4-12: SPI2 REGISTER MAP

SFR Name

SFR

Addr

Bit 15

Bit 14

Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

SPI2STAT

SPI2CON1

SPI2CON2

SPI2BUF

Legend:

0260 SPIEN

—

SPISIDL —

—

—

—

—

—

SPIROV

0262

—

—

—

DISSCK DISSDO MODE16 SMP

CKE

SSEN

CKP

0264 FRMEN SPIFSD FRMPOL —

—

—

—

—

—

—

0268

SPI2 Transmit and Receive Buffer Register

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

—

MSTEN

—

Bit 4

Bit 3

Bit 2

—

—

—

SPRE<2:0>

—

—

—

Bit 1

Bit 0

All

Resets

SPITBF SPIRBF

PPRE<1:0>

FRMDLY —

0000

0000

0000

0000

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