DSPIC33FJ32GP302T-I/SO 데이터 시트보기 (PDF) - Microchip Technology

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DSPIC33FJ32GP302T-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

6.1 System Reset

The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/

X04, and dsPIC33FJ128GPX02/X04 family of devices

have two types of Reset:

• Cold Reset

• Warm Reset

A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the

FNOSC configuration bits in the FOSC device

configuration register selects the device clock source.

A warm Reset is the result of all other reset sources,

including the RESET instruction. On warm Reset, the

device will continue to operate from the current clock

source as indicated by the Current Oscillator Selection

(COSC<2:0>) bits in the Oscillator Control

(OSCCON<14:12>) register.

The device is kept in a Reset state until the system

power supplies have stabilized at appropriate levels

and the oscillator clock is ready. The sequence in

which this occurs is detailed below and is shown in

Figure 6-2.

1. POR Reset: A POR circuit holds the device in

Reset when the power supply is turned on. The

POR circuit is active until VDD crosses the VPOR

threshold and the delay TPOR has elapsed.

2. BOR Reset: The on-chip voltage regulator has

a BOR circuit that keeps the device in Reset

until VDD crosses the VBOR threshold and the

delay TBOR has elapsed. The delay TBOR

ensures that the voltage regulator output

becomes stable.

3. PWRT Timer: The programmable power-up

timer continues to hold the processor in Reset

for a specific period of time (TPWRT) after a

BOR. The delay TPWRT ensures that the system

power supplies have stabilized at the appropri-

ate level for full-speed operation. After the delay

TPWRT has elapsed, the SYSRST becomes

inactive, which in turn enables the selected

oscillator to start generating clock cycles.

4. Oscillator Delay: The total delay for the clock to

be ready for various clock source selections is

given in Table 6-1. Refer to Section 9.0

“Oscillator Configuration” for more

information.

5. When the oscillator clock is ready, the processor

begins execution from location 0x000000. The

user application programs a GOTO instruction at

the reset address, which redirects program

execution to the appropriate start-up routine.

6. The Fail-safe clock monitor (FSCM), if enabled,

begins to monitor the system clock when the

system clock is ready and the delay TFSCM

elapsed.

TABLE 6-1: OSCILLATOR DELAY

Oscillator Mode

Oscillator

Startup Delay

Oscillator Startup

Timer

PLL Lock Time

Total Delay

FRC, FRCDIV16,

TOSCD

—

FRCDIVN

—

TOSCD

FRCPLL

TOSCD

—

TLOCK

TOSCD + TLOCK

XT

TOSCD

TOST

—

TOSCD + TOST

HS

TOSCD

TOST

—

TOSCD + TOST

EC

—

—

—

—

XTPLL

TOSCD

TOST

TLOCK

TOSCD + TOST + TLOCK

HSPLL

TOSCD

TOST

TLOCK

TOSCD + TOST + TLOCK

ECPLL

—

—

TLOCK

TLOCK

SOSC

TOSCD

TOST

—

TOSCD + TOST

LPRC

TOSCD

—

—

TOSCD

Note 1: TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a

10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.

DS70292D-page 82

Preliminary

 2009 Microchip Technology Inc.

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