QL7180-6PS484C 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL7180-6PS484C

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

EclipsePlus Family Data Sheet Rev. A

Figure 8: Logic Cell Flip-Flop Timings—Second Waveform

CLK

D

tSU

tHL

Q

tCO

Figure 9: EclipsePlus Global Clock Structure

Quad net

Clock Segment

tPGCK

tBGCK

Table 7: Eclipse Global Clock Tree Delays

Parameter

Global clock pin delay to quad net

Value (ns)

Max. Rise

Max. Fall

0.990

1.386

Global clock buffer delay (quad net to flip flop)

0.534

1.865

© 2006 QuickLogic Corporation

www.quicklogic.com

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